Semiconductor memory element, semiconductor memory arrangement, method for fabricating a semiconductor memory element and method for operating a semiconductor memory element

ABSTRACT

A semiconductor memory element has a substrate, in which a source region and a drain region are formed, a floating gate electrically insulated from the substrate, and a tunnel barrier arrangement, via which charging or discharging of the floating gate can be performed. It is possible to alter the conductivity of a channel between source and drain regions by charging or discharging the floating gate. A source line is electrically conductively connected to the source region and controls the charge transmission of the tunnel barrier arrangement.

CROSS REFERENCE TO RELATED APPLICATION(S)

This Utility Patent Application claims the benefit of the filing date ofApplication No. DE 101 43 235.6, filed Sep. 4, 2001 and InternationalApplication No. PCT/DE02/03220, filed Sep. 2, 2002, both of which areherein incorporated by reference.

BACKGROUND

The invention relates to a semiconductor memory element, a semiconductormemory element arrangement, a method for fabricating a semiconductormemory element and a method for operating a semiconductor memoryelement.

Some essential parameters of a semiconductor memory element are theretention time for which the memory content stored in the semiconductormemory element is preserved, the write time required for programming inthe memory content, and the write voltages required for programming inthe memory content.

A known semiconductor memory element is the DRAM memory element(DRAM=Dynamic Random Access Memory) which, although having relativelyfast write times of a few nanoseconds, has only short retention times onaccount of unavoidable leakage currents, so that the RAM memory elementhas to be recharged at regular time intervals of about 100 ms.

By contrast, although the so-called EEPROM memory element(EEPROM=Electrically Erasable Programmable Read Only memory) enablesrelatively long retention times of a number of years, the write timesrequired for programming in the memory content are significantly longerthan in the case of the RAM memory element.

There is therefore a need for semiconductor memory elements in whichfast write times (of about 10 nanoseconds) are combined with longretention times (of more than one year) and low write voltages.

K. K. Likharev, “Layered tunnel barriers for non-volatile memorydevices”, Applied Physics Letters Vol. 73, pages 2137–2139 has proposeda so-called “crested barrier” memory element, in which a floating gateis charged or discharged via a serial arrangement of (typically three)tunnel barriers, the tunnel barriers having a profiled (=“crested”)form. In this case, the tunnel barriers are not formed in the customarymanner in the form of a square-wave potential with a constant height ofthe potential barrier, but rather are profiled by means of “peaks”.

Since, compared with a conventional tunnel barrier, such a “profiled”tunnel barrier has a greater charge transmission and a greatersensitivity for the voltage present, relatively fast write times can beachieved theoretically in any case with such a “crested barrier”semiconductor memory element. However, the write voltages required forwriting are relatively large, i.e. approximately greater than 10 V.

K. Nakazato et al., “PLED—Planar Localized Electron Devices”, IEDM pages179–182 has disclosed a proposal for a so-called PLED memory element(PLED=Planar Localized Electron Device). In this case data is written orerased by fast charging or discharging of a floating gate via a multipletunnel barrier (MTJ=Multiple Tunnel Junction), the transmission of themultiple tunnel barrier being controlled by means of a side gateelectrode. For reading data, depending on the conductivity state of thechannel running below the floating gate between a source terminal and adrain terminal, a current flow is detected in the channel (correspondingto a “1” bit) or is not detected (corresponding to a “0” bit). In thecase of the PLED memory element, it is possible to achieve short writetimes (similar to those of a RAM memory element) and long retentiontimes (similar to those of an EEPROM memory element). Moreover, therequired write voltages are significantly lower than in the case of the“crested barrier” memory element mentioned above.

However, since a further terminal is required for the side gateelectrode for controlling the transmission of the tunnel barrier inaddition to the source, drain and data terminals, the PLED memoryelement is a 4-terminal arrangement. On account of this 4-terminalarrangement, the PLED memory element has relatively large dimensionsand, consequently, is not ideal for ULSI applications (ULSI=Ultra LargeScale Integration).

SUMMARY

One embodiment of, the invention addresses the problem of providing asemiconductor memory element, a semiconductor memory elementarrangement, a method for fabricating a semiconductor memory element anda method for operating a semiconductor memory element that has bettersuitability for ULSI applications in conjunction with enabling fastwrite times, long retention times and low write voltages.

In one embodiment of the invention, semiconductor memory element has asubstrate, in which at least one source region and at least one drainregion are formed. A floating gate is electrically insulated from thesubstrate.

Furthermore, a tunnel barrier arrangement is provided, via whichelectrical charge can be fed to the floating gate or can be dissipatedfrom the latter, it being possible to alter the conductivity of achannel between the source and drain regions by charging or dischargingthe floating gate.

Moreover, means for controlling the charge transmission of the tunnelbarrier arrangement is provided, which has a source line that iselectrically conductively connected to the source region.

By virtue of the fact that the means for controlling the chargetransmission of the tunnel barrier arrangement has a source line that iselectrically conductively connected to the source region, the sourceline can be used, on the one hand, for current transport when writing toor reading from the semiconductor memory element and, on the other hand,for controlling the charge transmission of the multiple tunnel barrier.Consequently, unlike in the case of the PLED memory element describedabove, there is no need for an additional terminal for a side gate whichcontrols the charge transmission.

In other words, by virtue of the fact that the charge transmission ofthe tunnel barrier arrangement is controlled via the source line, itsuffices, in the case of the invention's construction of thesemiconductor memory element, to provide, for operation, a source line,a data line and a word line to which different voltages can be appliedin each case for writing, reading and erasing.

The semiconductor memory element according to one embodiment of theinvention thus has a 3-terminal arrangement and, on account of theassociated narrower construction, is better suited in particular to ULSIapplications than a 4-terminal arrangement, as represented e.g. by thePLED memory element described above. At the same time, the semiconductormemory element according to the invention manages with significantlylower write voltages than, for instance, the abovementioned “crestedbarrier” memory element.

The tunnel barrier arrangement in one embodiment has a layer stack withan alternating layer sequence of semiconducting and insulating layersfor the purpose of forming a multiple tunnel barrier. In this case, thesource line extends from the source region parallel to the stackdirection of the layer stack of the multiple tunnel barrier. The sourceline additionally has doped polysilicon. As an alternative, the sourceline may have metal of aluminium, copper, or titanium nitride.

In accordance with one embodiment, the semiconducting layers of thelayer stack have undoped polysilicon, and the insulating layers havesilicon nitride or silicon dioxide.

In this case, the semiconducting layers may have a thickness in therange of typically 10 to 100 nm, and more specifically, in the range of30 to 50 nm. The insulating layers may have a thickness in the range oftypically 2 to 10 nm, and more specifically, in the range of 2 to 6 nm.

As an alternative, the semiconducting layers may also have amorphoussilicon.

The tunnel barrier arrangement may be electrically connected to a wordline on its side remote from the floating gate, by means of which wordline a voltage pulse can be applied via the tunnel barrier arrangementto the floating gate for the purpose of charging the latter and for thepurpose of inverting the channel between source region and drain region.

In a semiconductor memory element arrangement according to oneembodiment of the invention, a plurality of semiconductor memoryelements according to the invention are arranged in a matrix-like mannerin a plurality of rows and columns, the semiconductor memory elementsbelonging to a column having a common source line which is electricallyconductively connected to the source regions of said semiconductormemory elements and via which the charge transmission of the tunnelbarrier arrangements belonging to said semiconductor memory elements canbe controlled.

In this case, the source line respectively assigned to a semiconductormemory element in a row may form a bit line of a semiconductor memoryelement that is adjacent in the same row. In this way, it is possible torealize particularly high storage densities of 4×f² (f=“minimum featuresize”).

However, it is also possible for a common source line to be assigned ineach case to two semiconductor memory elements that are arrangedadjacent in the same row. In this case, the source line is arrangedsymmetrically, i.e. at the same distance with respect to the layerstacks that are adjacent on the left and right of the source line, forforming the tunnel barrier arrangement, as a result of which thefabrication process of the semiconductor memory element arrangement issimplified.

A method for fabricating a semiconductor memory element in accordancewith one embodiment of the invention has the following steps:

-   -   formation of at least one source region and at least one drain        region in a substrate;    -   formation of a floating gate that is electrically insulated from        the substrate;    -   formation of a tunnel barrier arrangement, via which electrical        charge can be fed to the floating gate or dissipated from the        latter, it being possible to alter the conductivity of a channel        between the source and drain regions by charging or discharging        the floating gate; and    -   a source line that is electrically conductively connected to the        source region and serves for controlling the charge transmission        of the tunnel barrier arrangement being formed adjacent to the        tunnel barrier arrangement.

In one embodiment, the tunnel barrier arrangement is formed as a layerstack with an alternating layer sequence of semiconducting andinsulating layers for the purpose of forming a multiple tunnel barrier.

The source line is formed from the source region parallel to the stackdirection of the layer stack of the multiple tunnel barrier.

In one embodiment, the step of formation of a source line that iselectrically conductively connected to the source region has thefollowing steps:

-   -   application of a first semiconducting layer on an insulating        layer that covers the tunnel barrier arrangement and the source        region;    -   performance of a directional implantation for doping that region        of the first semiconducting layer which is applied on the        insulating layer that covers the multiple tunnel barrier;    -   uncovering of the source region by partial removal of the first        semiconducting layer that covers the source region and of the        insulating layer;    -   removal of the non-doped regions of the first semiconducting        layer with the insulating layer being partially uncovered; and    -   selective application of a second semiconducting layer to the        source region and the doped region of the first semiconducting        layer.

In one embodiment, the first and second semiconducting layers are formedfrom polysilicon and the insulating layer is preferably formed fromsilicon dioxide (SiO₂) or silicon nitride (Si₃N₄).

In one method for operating a semiconductor memory element which has asubstrate with at least one source region formed therein and at leastone drain region formed therein, a floating gate electrically insulatedfrom the substrate, and a tunnel barrier arrangement, electrical chargebeing fed to the floating gate or dissipated from the latter via thetunnel barrier arrangement, the conductivity of a channel between sourceand drain regions being altered by charging or discharging the floatinggate, and the charge transmission of the tunnel barrier arrangementbeing controlled via a source line that is electrically conductivelyconnected to the source region.

In one embodiment of writing data to the semiconductor memory element, avoltage in the range of +(2–3) volts is applied to the source line and avoltage of at most ±1 volt is applied to a word line which iselectrically connected to the tunnel barrier arrangement on its sideremote from the floating gate.

The voltage of +(2–3) volts present on the source line exponentiallyincreases the transmission of the tunnel barrier arrangement formed bythe layer stack and enables electrical charge to be fed to or dissipatedfrom the floating gate and thus an inversion of the channel situatedbetween source and drain regions.

For reading data of the semiconductor memory element a voltage in therange of +(0.5–1) volt is applied to a bit line that is electricallyconductively connected to the drain region; and a voltage in the rangeof +(3–5) volts is applied to a word line which is electricallyconnected to the tunnel barrier arrangement on its side remote from thefloating gate.

On account of the capacitive coupling, the voltage of +(3–5) voltspresent on the word line corresponds to a voltage of typically about+1.5 volts between floating gate and the channel between source regionand drain region, so that the capacitive punch-through from the wordline to the floating gate and the channel between source and drainregions suffices to put the read-out transistor into the on state.Consequently, when a low voltage of +(0.5–1) volt is applied to the bitline, depending on inverted or non-inverted state of the channel, acurrent flow is detected in the channel (corresponding to a “1” bit) oris not detected (corresponding to a “0” bit).

Exemplary embodiments of the invention are illustrated in the figuresand are explained in more detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a to 1 g illustrate a semiconductor memory element according tothe invention in accordance with an exemplary embodiment of theinvention at different states during its fabrication;

FIG. 2 illustrates a diagrammatic side view of a semiconductor memoryelement in accordance with a first preferred embodiment;

FIG. 3 shows a diagrammatic illustration of a semiconductor memoryelement arrangement of six semiconductor memory elements constructed inaccordance with FIG. 2, in plan view;

FIG. 4 illustrates a programming example for the semiconductor memoryelement from FIG. 2;

FIG. 5 illustrates a diagrammatic side view of a semiconductor memoryelement in accordance with a second preferred embodiment; and

FIG. 6 illustrates a diagrammatic illustration of a semiconductor memoryelement arrangement of six semiconductor memory elements constructed inaccordance with FIG. 5, in plan view.

DETAILED DESCRIPTION

In accordance with FIG. 1 a, a layer 102 made of silicon dioxide with athickness of about 6–10 nm and a layer 103 made of doped polysiliconwith a thickness of 50 nm are grown one after the other in order tofabricate a semiconductor memory element 100 on a silicon substrate 101.The layer 103 serves for forming a floating gate of the semiconductormemory element 100.

Barrier layers 104, 106 and 108 made of silicon nitride (Si₃N₄) andlayers 105, 107 and 109 made of undoped polysilicon are applied in analternating layer sequence on the layer 103, this preferably beingperformed by means of chemical vapour deposition (CVD) or thermalnitriding. The layer stack formed from the layers 103–108 serves forforming a multiple tunnel barrier, it being possible for the multipletunnel barrier also to have a different number of barrier layers andpolysilicon layers, but at least one barrier layer and two polysiliconlayers separated by the barrier layer.

In the exemplary embodiment illustrated, the undoped polysilicon layers105 and 107 have a thickness of 40 nm, the doped polysilicon layer 109has a thickness of 50 nm, the barrier layers 104 and 108 have athickness of 2 nm and the barrier layer 106 has a thickness ofapproximately 5 nm.

In a next step, in accordance with FIG. 1 b, after the etching of the“layer stack” of polysilicon and silicon nitride layers 103–109, with asilicon dioxide layer 110 having a thickness of about 6 nm, adirectional arsenic implantation with a dose of about 10²⁰ cm⁻³ isperformed for the purpose of forming source and drain regions 111, 112in the substrate 101, symbolized by means of arrows 123 in FIG. 1 b. Inthis case, the silicon dioxide layer 110 serves to prevent doping atomsfrom penetrating into the layer stack 103–109.

Afterward, in accordance with FIG. 1 c, a layer 113 made of polysilicon,whose thickness corresponds to approximately f/4 (f=minimum featuresize), is applied to the silicon dioxide layer 110 and the silicondioxide layer 102 extending between the layer stacks 103–109.

In a next step, an obliquely directed implantation of boron atoms 114 isperformed, as can be seen from FIG. 1 d, (i.e. only onto the respectiveregions shown on the right in the trenches in FIG. 1 d). After thisone-sided boron implantation, polysilicon spacers 115 are formed fromthe layer 113 made of polysilicon by means of an etching step, whereupona rapid thermal treatment (RTP=rapid thermal process) is performed inorder to achieve activation of the boron doping atoms at the correctlattice sites.

Afterward, the silicon dioxide layer 102 extending between thepolysilicon spacers 115 is partially etched away (FIG. 1 d), whereupon afurther wet-chemical etching step is performed using potassium hydroxide(KOH). This etching step serves for removing only the non-doped regionsof the polysilicon spacers 115 (i.e. the respective regions shown on theleft in the trenches in FIG. 1 d) with the underlying silicon dioxidelayer 110 being uncovered.

In a next step, in accordance with FIG. 1 e, a selective epitaxy ofpolysilicon is performed, polysilicon being applied only in the regionsin which there is no silicon dioxide, i.e. in the regions shown on theright in FIG. 1 e within each trench structure and also above the sourceand drain regions 111, 112, since the silicon dioxide layer 110 haspreviously been removed there. Consequently, a layer 116 and 117,respectively, made of polysilicon is applied on these regions, thethickness of the layer 117 above the source and drain regions beingabout 10 nm, but in any event amounting to at least the thickness of thesurrounding silicon dioxide layer 110.

Afterward, in accordance with FIG. 1 e, an obliquely directedimplantation of phosphorus ions 118 is performed. In a next step,silicon dioxide 119 is applied to fill the trench structure, whereupon achemical mechanical polishing (CMP) is performed.

In a next step, in accordance with FIG. 1 f, the topmost region of thepolysilicon layers 116 and 117, which region lies at the level of thepolysilicon layer 109, is partly etched back, whereupon thecorresponding region is again filled with silicon dioxide 119 and afurther CMP step is performed.

Afterward, a titanium/titanium nitride layer 120 is applied for thepurpose of forming a diffusion barrier on the layers 119 and 109, and onit in turn there are successively deposited a layer 121 made of tungstenand a layer 122 of silicon nitride (Si₃N₄) for the purpose of formingthe semiconductor memory element 100 illustrated in FIG. 1 g.

Afterward, the layer stack comprising the layers made of siliconnitride, tungsten and the barrier layer made of polysilicon is etcheddown to the layer 102 made of silicon dioxide. The layer made of siliconnitride, which is arranged on the layer made of tungsten, serves as ahard mask in this etching operation. By means of this etching step, thestructures are separated in the y-direction, i.e. in the directionperpendicular to the plane of the drawing from FIG. 1 g.

In accordance with FIG. 2, a semiconductor memory element 200 fabricatedin accordance with the method described above has source and drainregions 201, 202 which are formed in a substrate (not illustrated) andbetween which extends a channel (not illustrated) with variableelectrical conductivity in the substrate.

Furthermore, the semiconductor memory element 200 has a floating gate203 made of a polysilicon layer having a thickness of about 50 nm, onwhich a layer stack 204 with alternately successive silicon nitridelayers 205, 207 and 209 and polysilicon layers 206 and 208 issuccessively applied for the purpose of forming a multiple tunnelbarrier.

A tungsten layer 210 for forming a word line of the semiconductor memoryelement 200 is applied on the topmost silicon nitride layer 209.

In the region that does not adjoin the tungsten layer 210, the floatinggate 203 and the layer stack 204 are surrounded by a silicon dioxideregion 211, via which the semiconductor memory element 200 is insulatedfrom adjacent semiconductor memory elements. The silicon dioxide region211 has, in particular, a silicon dioxide layer 212, which insulates thefloating gate 203 from the substrate.

Furthermore, provision is made of a source line 213 made of n⁺-dopedpolysilicon which extends adjacent to the floating gate 203 and thelayer stack 204 from the source region 201, and a bit line 214 made ofn⁺-doped polysilicon which extends parallel to said source line on theopposite side of the floating gate 203 and of the layer stack 204 fromthe drain region 202.

In the case of the semiconductor memory element 200 which is illustratedin FIG. 2 and fabricated in accordance with the method illustrated inFIGS. 1 a–g, the position of the source line 213 is asymmetrical in sofar as said source line, as can be seen from FIG. 2, is arrangedsignificantly nearer to the layer stack 204 forming the tunnel barrierarrangement than to the corresponding layer stack situated on theopposite side of the source line 213 (i.e. on the left in FIG. 2).Although this increases the fabrication outlay compared with asymmetrical arrangement of the source line 213 (which will be describedin connection with FIG. 4), it is ensured, when suitable voltages areapplied to the source line, that exclusively the nearest adjacent tunnelbarrier arrangement is “opened”, i.e. the vertical transmission thereofis increased.

Moreover, in the exemplary embodiment of a semiconductor memory element200 as illustrated in FIG. 2, the source line 213 simultaneously servesas a bit line for an adjacent semiconductor memory element which isarranged on that side of the source line 213 which is remote from thefloating gate 203 (i.e. to the left of the source line 213 in FIG. 2).In this way, it is possible to realize particularly high storagedensities of 4×f² (f=“minimum feature size”).

FIG. 3 illustrates a grid structure 300 of a semiconductor memoryelement arrangement, in which floating gates 300 a . . . 300 d belongingto four semiconductor memory elements are arranged in a gridarrangement, each of the semiconductor memory elements 300 a–300 d beingconstructed identically to the semiconductor memory element 200 fromFIG. 2. Accordingly, a source line 301 runs adjacent to the floatinggates 300 a–300 b on the side thereof which is remote from the floatinggates 300 a–300 b, and a bit line 302 runs on the side thereof whichfaces the floating gates 300 a–300 b. A source line 303 in turn runs onthat side of the floating gates 300 c–300 d which is remote from thefloating gates 300 a–300 b.

The floating gates 300 a–300 d are surrounded by a silicon dioxideregion 304 and, in the interspaces remaining between adjacent floatinggates 300 a–300 d, are isolated by silicon dioxide layers 305 in orderto insulate adjacent semiconductor memory elements from one another.

In order to explain the method of operation of the semiconductor memoryelement 200, FIG. 4 illustrates a programming example of thesemiconductor memory element 200. Accordingly, the write process iseffected by applying a positive voltage of +2.5 volts to the source line213 in order to open the channel and applying a negative voltage of −1volt to the word line 210 (write line). Data are correspondingly erasedby applying a positive voltage of +1 volt to the word line 210 andapplying a positive voltage of +2.5 volts to the source line 213.

The voltage of +2.5 volts present on the source line 213 increases thecharge transmission of the tunnel barrier arrangement formed by thelayer stack 204 and enables electrical charge to be fed to or dissipatedfrom the floating gate 203 and thus an inversion of the channel situatedbetween source and drain regions 201, 202.

The read process is effected by applying a positive voltage of, forexample, +4 volts to the word line 210 and applying a low positivevoltage of, for example, +0.5 volt to the bit line 214. On account ofthe capacitive coupling, a voltage of about +1.5 volts between floatinggate 203 and the channel between source region 201 and drain region 202corresponds to the voltage of +4 volts present on the word line 210, sothat the capacitive punch-through from the word line 210 to the floatinggate 203 and the channel between source and drain regions 201, 202suffices to put the read-out transistor into the on state.

Consequently, when a low voltage of +0.5 volt is applied to the bitline, depending on the inverted or noninverted state of the channel, acurrent flow in the channel is detected (corresponding to a “1” bit) oris not detected (corresponding to a “0” bit).

FIG. 5 illustrates a semiconductor memory element 400 in accordance witha further embodiment of the invention. Like the semiconductor memoryelement 200, the semiconductor memory element 400 has source and drainregions 401 and 402, respectively, between which a floating gate 403 isarranged. A layer stack 404 with alternately successive silicon nitridelayers 405, 407 and 409 and polysilicon layers 406 and 408 is applied onthe floating gate 403 for the purpose of forming a multiple tunnelbarrier.

A tungsten layer 410 for forming a word line of the semiconductor memoryelement 400 is applied on the topmost silicon nitride layer 409.

In the region that does not adjoin the tungsten layer 410, the floatinggate 403 and the layer stack 404 are surrounded by a silicon dioxideregion 411, via which the semiconductor memory element 400 is insulatedfrom adjacent semiconductor memory elements. The silicon dioxide region411 has, in particular, a silicon dioxide layer 412, which insulates thefloating gate 403 from the substrate.

The semiconductor memory element 400 is adjoined by a furthersemiconductor memory element 400′, which, in a corresponding manner, hasa floating gate 413 and a layer stack 414 with alternately successivesilicon nitride layers 415, 417 and 419 and polysilicon layers 416 and418.

Furthermore, in the semiconductor memory element 400, provision is madeof a source line 420 made of n⁺-doped polysilicon which extends adjacentto the floating gate 403 and the layer stack 404 from the source region401. On the opposite side of the floating gate 403 and of the layerstack 404, the drain region 402 forms a bit line 421.

In contrast to the semiconductor memory element 200, in the case of thesemiconductor memory element 400, the bit line 421 does not form thesource line for the adjacent semiconductor memory element 400′, butrather is formed from this as a separate line. Rather, the adjacentsemiconductor memory element 400′ has a dedicated source line 422, whichis only partly illustrated in FIG. 5, so that the storage density of thesemiconductor memory element 400 is only 8×f². Unlike in the case of thesemiconductor memory element 200, however, in the case of thesemiconductor memory element 400, the source line 420 is arrangedsymmetrically, i.e. at the same distance from the layer stacks adjacenton the left and right of the source line 420. In this way, thefabrication process is simplified compared with the process described inFIGS. 1 a–g.

FIG. 6 illustrates a grid structure 500, in which floating gates 500 a .. . 500 d belonging to four semiconductor memory elements are connectedto one another in a grid arrangement, each of the semiconductor memoryelements 500 a–500 d being constructed identically to the semiconductormemory element 400 from FIG. 5. Accordingly, a source line 501 runsadjacent to the floating gates 500 a–500 b on the side thereof which isremote from the floating gates 500 c–500 d, and a bit line 502 runs onthe side thereof which faces the floating gates 300 c–300 d. A sourceline 303 in turn runs on that side of the floating gates 500 c–500 dwhich is remote from the floating gates 500 a–500 b.

The floating gates 500 a–500 d are surrounded by a silicon dioxideregion 504 and, in the interspaces remaining between adjacent floatinggates 500 a–500 d, are isolated by silicon dioxide layers 505 in orderto insulate adjacent semiconductor memory elements from one another.

The operation of the semiconductor memory element 400 or thesemiconductor memory element arrangement in accordance with FIG. 6essentially corresponds to that of the semiconductor memory element 200,but when a voltage of, for example, +2.5 volts is applied to the sourceline 420, both adjacent tunnel barrier arrangements are “opened”, i.e.their vertical transmission is increased. However, in the case of thesemiconductor memory element 400, too, selective writing or erasing canbe effected by applying a low voltage of e.g. +/−1 volt to therespective word line.

In all the exemplary embodiments illustrated, the source line can ineach case be used, on the one hand, for current transport when writingto or reading from the semiconductor memory element and, on the otherhand, for controlling the charge transmission of the multiple tunnelbarrier, so that there is no need for an additional terminal for a sidegate which controls the charge transmission through the multiple tunnelbarrier. Rather, the charge transmission of the tunnel barrierarrangement is controlled via the source line, so that the semiconductormemory element according to the invention has a 3-terminal arrangementand is thus particularly suitable for ULSI applications.

1. A semiconductor memory element, comprising: a substrate, in which atleast one source region and at least one drain region are formed; afloating gate electrically insulated from the substrate; a tunnelbarrier arrangement, via which electrical charge can be fed to thefloating gate or dissipated from the latter, it being possible to alterthe conductivity of a channel between the source and drain regions bycharging or discharging the floating gate; means for controlling thecharge transmission of the tunnel barrier arrangement; and wherein themeans for controlling the charge transmission of the tunnel barrierarrangement has a source line which is electrically conductivelyconnected to the source region extending from the source region parallelto the stack direction of the layer stack of the multiple tunnelbarrier.
 2. The semiconductor memory element of claim 1, the tunnelbarrier arrangement having a layer stack with an alternating layersequence of semiconducting and insulating layers for the purpose offorming a multiple tunnel barrier.
 3. The semiconductor memory elementof claim 1, the source line having doped polysilicon or a metal.
 4. Thesemiconductor memory element of claim 2, the semiconducting layers ofthe layer stack having undoped polysilicon.
 5. The semiconductor memoryelement of claims 2, the insulating layers of the layer stack havingsilicon nitride or silicon dioxide.
 6. The semiconductor memory elementof claims 2, the semiconducting layers of the layer stack having athickness in the range of 10 to 100 nm and the insulating layers havinga thickness in the range of 2 to 10 nm.
 7. The semiconductor memoryelement of claim 6, the semiconducting layers of the layer stack havinga thickness in the range of 30 to 50 nm and the insulating layers havinga thickness in the range of 2 to 6 nm.
 8. The semiconductor memoryelement of claims 1, the tunnel barrier arrangement being electricallyconnected to a word line on its side remote from the floating gate, bymeans of which word line a voltage pulse can be applied via the tunnelbarrier arrangement to the floating gate for the purpose of charging thelatter and for the purpose of inverting the channel between sourceregion and drain region.
 9. The semiconductor memory element of claim 1and at least one additional like semiconductor memory element arrangedin a matrix-like manner in a plurality of rows and columns, thesemiconductor memory elements belonging to a column having a commonsource line which is electrically conductively connected to the sourceregions of said semiconductor memory elements and via which the chargetransmission of the tunnel barrier arrangements belonging to saidsemiconductor memory elements can be controlled.
 10. The semiconductormemory element arrangement of claim 9, the source line respectivelyassigned to a semiconductor memory element in a row forming a bit lineof a semiconductor memory element that is adjacent in the same row. 11.The semiconductor memory element arrangement of claim 9, a common sourceline being assigned in each case to two semiconductor memory elementsthat are arranged adjacent in the same row.
 12. A method for fabricatinga semiconductor memory element comprising: forming at least one sourceregion and at least one drain region in a substrate; forming a floatinggate that is electrically insulated from the substrate; forming a tunnelbarrier arrangement, via which electrical charge can be fed to thefloating gate or dissipated from the latter, it being possible to alterthe conductivity of a channel between the source and drain regions bycharging or discharging the floating gate; and providing a source linethat is electrically conductively connected to the source region andserves for controlling the charge transmission of the tunnel barrierarrangement being formed adjacent to the tunnel barrier arrangement,said source line being formed from the source region parallel to thestack direction of the layer stack of the multiple tunnel barrier. 13.The method of claim 12, the tunnel barrier arrangement being formed as alayer stack with an alternating layer sequence of semiconducting andinsulating layers for the purpose of forming a multiple tunnel barrier.14. The method of claim 12, the step of formation of a source line thatis electrically conductively connected to the source region comprising:application of a first semiconducting layer on an insulating layer thatcovers the tunnel barrier arrangement and the source region; performanceof a directional implantation for doping that region of the firstsemiconducting layer which is applied on the insulating layer thatcovers the multiple tunnel barrier; uncovering of the source region bypartial removal of the first semiconducting layer that covers the sourceregion and of the insulating layer; removal of the non-doped regions ofthe first semiconducting layer with the insulating layer being partiallyuncovered; and selective application of a second semiconducting layer tothe source region and the doped region of the first semiconductinglayer.
 15. The method of claim 14, the first and second semiconductinglayers being formed from polysilicon and the insulating layer beingformed from silicon dioxide.
 16. A method for operating a semiconductormemory element which has a substrate with at least one source regionformed therein and at least one drain region formed therein, a floatinggate electrically insulated from the substrate, and a tunnel barrierarrangement, comprising: feeding an electrical charge to the floatinggate or dissipated from the latter via the tunnel barrier arrangement;altering the conductivity of a channel between source and drain regionsby charging or discharging the floating gate; and controlling the chargetransmission of the tunnel barrier arrangement via a source line that iselectrically conductively connected to the source region, the sourceline being formed from the source region parallel to the stack directionof the layer stack of the multiple tunnel barrier.
 17. The method ofclaim 16, for writing data of the semiconductor memory element furthercomprising: applying a voltage in the range of +(2–3) volts to thesource line; and applying a voltage of at most ±1 volt to a word linewhich is electrically connected to the tunnel barrier arrangement on itsside remote from the floating gate.
 18. The method of claim 16, forreading data of the semiconductor memory element further comprising:applying a voltage in the range of +(0.5–1) volt to a bit line that iselectrically conductively connected to the drain region; and applying avoltage in the range of +(3–5) volts to a word line which iselectrically connected to the tunnel barrier arrangement on its sideremote from the floating gate.